Nvm Digital Design Engineer

Qualifications:
MSEE or BSEE with equivalent relevant experience.
7+ years of industry experience that includes transistor level design, simulation, and layout as well as mixed signal design integration.

Experience with verilog RTL design, functional verification (UVM), synthesis, and pre/post-layout analysis using industry-standard simulation and synthesis tools.

Preference will be given to those with proven skills in the following areas:

Experience in using OTP/MTP/eFLASH NVM in product development.

A good understanding of microprocessor and memory subsystem design requirements;

Transistor level simulation using SPICE (or equivalent) analysis tools
Experience with Cadence design and layout tool suite, including digital place and route and layout parasitic extraction

Brief Job Description:

The NVM Digital Design Engineer will be responsible for the integration, support, and deployment of non-volatile memory (NVM) IP to support a wide range of ADI products.

Pro-active communication of NVM Team message to product development teams;

Actively support the design of memory-controllers for supported NVM IP and to work closely with development teams to ensure the IP functions as expected within the end-user product;

Development of datasheets, integration guides, and design views necessary to correctly use NVM-IP within the ADI design flows;

Work with product development teams for supported NVM IP and ensure alignment with ADI NVM standards and best practices for probe/test of integrated NVM;

Transistor level design analysis and optimization of internally developed NVM-IP for a variety of target processes and operating conditions;

Support the development of QA flows for the release process of the NVM IP;

Support new NVM IP selection process;

Support NVM vendor interactions and issue resolution;

Drive NVM review process with development teams on integrated NVM IP;

Support NVM education through workshops/newsletters/Special Interest Groups;

Support ADI’s global development teams.